Selective Deposition Technology
2024-12-16
As semiconductor manufacturing technology continues to advance, the challenge of creating smaller, faster, and more energy-efficient chips becomes increasingly significant, particularly with the advent of Gate-All-Around (GAA) transistors and more advanced Complementary FET (CEF) transistors. To further optimize these processes, a technique known as selective deposition has emerged. This technology achieves its goals by precisely controlling the deposition of materials within specific areas, primarily dividing into two forms: Deposition on Demand (DoD) and Material on Demand (MoD).
Deposition on Demand (DoD)
The essence of the DoD process lies in its ability to accurately deposit materials only where needed, while avoiding unnecessary coverage of non-target areas.
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Surface Preparation: The substrate is thoroughly cleaned and pre-treated to ensure that materials adhere well during the subsequent deposition process.
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Selective Inhibitor Layer Application: A protective inhibitor layer is then applied to areas where material deposition is not desired, preventing material deposition in these regions. (i) Inhibitors for metals and oxides: Thiols, alkynes, aromatic amines (ii) Inhibitors for oxides/sulfides and other oxides/sulfides: Carboxylic acids, β-diketones (iii) Inhibitors for oxides and metals: Methoxysilanes
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Selective Deposition: Utilizing techniques to accurately deposit the required materials on the prepared surface.
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Inhibitor Layer Removal: The final step involves removing the previously added inhibitor layer, completing the entire deposition process while maintaining the structure intact and undamaged.
Material on Demand (MoD)
The MoD process focuses on depositing various types of materials, such as tungsten (W) or molybdenum (Mo), at specified locations according to different requirements, thereby creating more complex and powerful interconnect structures. The specific implementation steps are as follows:
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Initial Material Deposition: Begin by depositing a layer of base material, such as tungsten or molybdenum.
2. Surface Cleaning: Any impurities on the surface are then removed to ensure that the material to be deposited next will bond securely.
3. Inhibitor Layer Application and Surface Preparation: The inhibitor layer technique is also used to restrict material deposition to predetermined areas.
4. Selective ALD Deposition: ALD technology is employed again, this time to add a layer of tungsten or molybdenum as a liner for copper interconnects, enhancing conductivity.
5. Inhibitor Layer Removal: The final stage involves removing all excess inhibitor layers, ensuring that the resulting interconnect structure is both compact and reliable.
We at Semicorex specialize in SiC/TaC coated graphite solutions applied in thin film deposition and further semiconductor manufacturing, if you have any inquiries or need additional details, please don't hesitate to get in touch with us.
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